Logic devices such as FPGAs are used to implement large systems that may include million of gates and megabits of embedded memory. The complexity of large systems often requires the use of EDA tools to create and optimize a design for the system onto physical target devices. Among the procedures performed by EDA tools in a computer aided design (CAD) flow are synthesis, mapping, placement, and routing.
Typically during synthesis, a designer inputs a description of the system into the EDA tool. Traditionally, the description of the system includes a register transfer level (RTL) description to describe the operation of synchronous digital circuits. In RTL design, a circuit's behavior is defined in terms of the flow of signals between hardware registers and the logical operations performed on those signals. RTL abstraction is used in hardware description languages such as Verilog and very-high-speed integrated circuit (VHSIC) hardware description language (VHDL) to create high-level representations of a circuit, from which lower-level representations and can be derived.
Many digital signal processing (DSP) circuits are targeted for scalable implementations with varying configurations of channel counts, clock frequencies, and other parameters. When a change is made to one of these aspects of a design to the DSP circuit, many other aspects of the design for the DSP circuit would have to be changed manually to support it. For example, the manual widening of data paths and stepping and repeating of components in the design would require additional time and effort from the designer.